FEEDBACK_MODE=FLOP, POLARITY_SEL=IDACA_POL, CMP_PHASE=FULL, CMP_MODE=CSD, CSDCMP_EN=OFF
CSD Comparator configuration
| CSDCMP_EN | CSD Comparator Enable 0 (OFF): Disable comparator, output is zero 1 (ON): On, regular operation. Note that CONFIG.LP_MODE determines the power mode level |
| POLARITY_SEL | Select which IDAC polarity to use to detect CSDCMP triggering 0 (IDACA_POL): Use idaca_pol (firmware setting with CSX and optionally DSI mixed in) to determine the direction, this is the most common use-case, used for normal CSD and normal CSX 1 (IDACB_POL): Use idacb_pol (firmware setting with optional DSI mixed in) to determine the direction, this is only used for normal CSD if IDACB is used i.s.o. IDACA (not common) 2 (DUAL_POL): Use the expression (csd_sense ? idaca_pol : idacb_pol) to determine the direction, this is only useful for the CSX with DUAL_IDAC use-case |
| CMP_PHASE | Select in what phase(s) the comparator is active, typically set to match the BAL_MODE of the used IDAC. Note, this also determines when a bad conversion is detected, namely at the beginning and end of the comparator active phase (also taking into account FILTER_DELAY and non-overlap). 0 (FULL): Comparator is active from start of Phi2 and kept active into Phi1. Intended usage: legacy CSD for balancing over a full csd_sense period (non-overlap should be turned off) 1 (PHI1): Comparator is active during Phi1 only. Currently no known use-case. 2 (PHI2): Comparator is active during Phi2 only. Intended usage: CSD Low EMI. 3 (PHI1_2): Comparator is activated at the start of both Phi1 and Phi2 (non-overlap should be enabled). Intended usage: CSX, or Full-Wave. |
| CMP_MODE | Select which signal to output on dsi_sample_out. 0 (CSD): CSD mode: output the filtered sample signal on dsi_sample_out 1 (GP): General Purpose mode: output the unfiltered sample unfiltered comparator output, either asynchronous or flopped. |
| FEEDBACK_MODE | This bit controls whether the output directly from the comparator (csdcmp_out) or the flopped version (csdcmp_out_ff) is used. For CSD operation, the selected signal controls the IDAC(s), in GP mode the signal goes out on dsi_sample_out. 0 (FLOP): Use feedback from sampling flip-flop (used in most modes). 1 (COMP): Use feedback from comparator directly (used in single Cmod mutual cap sensing only) |
| AZ_EN | Auto-Zero enable, allow the Sequencer to Auto-Zero this component |